View AD7657-1-15_9044704.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

250 ksps, 6 - channel, simultaneous sampling, bipolar, 16 - /14 - /12 - bit adc data sheet ad7656 - 1/ad7657 - 1/ad7658 - 1 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, no r for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. tradem arks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 C 2012 analog devices, inc. all rights reserved. features pin and software compatible with ad7656/ad7657/ad7658 featuring reduced decoupling requirements 6 independent adcs true bipolar analog inputs pin - /software - selectable ranges: 10 v, 5 v fast throughput rate: 250 ksps i cmos process technology low power 140 mw at 250 ksps with 5 v supplies high noise performance with wide bandwidth 88 db snr at 1 0 khz input frequency on - chip reference and reference buffers high speed parallel , serial, and daisy - chain interface modes high speed serial interface spi / qspi? / microwire? /dsp compatible standby mode: 31 5 w max imum 64- lead lqfp applications power line monitoring and measuring systems instrumentation and control systems multi axis positioning systems functional block dia gram v ss dgnd v dd ref convst a convst b convst c output drivers output drivers output drivers output drivers control logic buf buf buf agnd t/h t/h t/h t/h t/h t/h clk osc av cc dv cc v1 v2 v3 v4 v5 v6 ser/ p ar se l cs v drive stby db8/dout a db9/dout b db10/dout c db6/sclk rd wr/ref en/dis data/ control lines ad7656-1/ad7657-1/ad7658-1 16-/14-/ 12-bit sar 16-/14-/ 12-bit sar 16-/14-/ 12-bit sar 16-/14-/ 12-bit sar 16-/14-/ 12-bit sar 16-/14-/ 12-bit sar 07017-001 figure 1. general description the ad7656 - 1/ad7657 - 1/ad7658 - 1 1 are reduced decoupling pin - and software - compatible versions of ad7656/ad7657/ad7658 . the ad7656 - 1/ad7657 - 1/ad7658 - 1 devices contain six 16 - / 14- /12 - bit, fast, low power successive approximation adcs in a package designed on the i cmos ? process (industrial cmos). i cmos is a process combining high voltage silicon with submicron cmos and complementary bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts could achieve. unlike analog ics us ing conven - tional cmos processes, i cmos components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size. the ad7656 - 1/ad7657 - 1/ad7658 - 1 feature throughput rates of up to 250 ksps. the parts contain low noise, wide bandwidth track - and - hold amplifiers that can handle input frequencies up to 4.5 mhz. the conversion process and data acquisition are controlled using the convst signals and an internal oscillator. three convst pin s (convst a, convst b, and convst c) allow independent, simultaneous sampling of the three adc pairs. the ad7656 - 1/ad7657 - 1/ad7658 - 1 have a high speed parallel and serial interface, allowing the devices to interface with microprocessors or dsps. when the s erial interface is selected , each part has a daisy - chain feature that allows multiple adcs to connect to a single serial interface. the ad7656 - 1/ad7657 - 1/ ad7658 - 1 can accommodate true bipolar input signals in the 4 v ref and 2 v ref ranges. each ad765 6 - 1/ ad7657 - 1/ ad7658 - 1 also contain s an on - chip 2.5 v reference. product highlights 1. six 16 - /14 - /12 - bit, 250 ksps adcs on board. 2. six true bipolar, high impedance analog inputs. 3. high speed parallel and serial interfaces. 4. reduced decoupling requirements and reduced bill of materials cost compared with the ad7656/ad7657/ ad7658 devices. 1 protected by u.s. patent no. 6,731,2 32.
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diag ram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision histor y ............................................................................... 2 specifications ..................................................................................... 3 ad7656 - 1 ...................................................................................... 3 ad7657 - 1 ...................................................................................... 5 ad7658 - 1 ...................................................................................... 7 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 14 terminology .................................................................................... 18 theory of op eration ...................................................................... 20 converter details ....................................................................... 20 adc transfer function ............................................................. 21 interna l/external reference ...................................................... 21 typical connection diagram ................................................... 21 driving the analog inputs ........................................................ 22 interface options ........................................................................ 22 software selection of adcs ...................................................... 24 changing the analog input range ( h /s se l = 0) ................ 25 changing the analog input range ( h /s sel = 1) ................ 25 serial read operation ................................................................ 25 daisy - chain mode (dcen = 1, ser/ pa r sel = 1) ............. 27 application hints ........................................................................... 29 la yout .......................................................................................... 29 power supply configuration ..................................................... 29 outline dimensions ....................................................................... 30 orde ring guide .......................................................................... 30 revision history 3/12 rev. c to rev. d changes to figure 28 ...................................................................... 22 11 /10 rev. b to rev. c added power supply configuration section .............................. 29 added figure 39 .............................................................................. 29 6 /10 rev. a to rev. b changes to dc accuracy parameter, table 1 ............................... 3 changes to dc accuracy parameter, table 2 ............................... 5 change to dc accuracy parameter , table 3 ................................. 7 added %fsr to terminology section ......................................... 19 3 /09 rev. 0 to rev. a changes to features .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 3 ............................................................................. 7 changes to tab le 4 ............................................................................. 9 changes to absolute maximum ratings table .......................... 10 changes to pin functions description table ............................. 11 changes to figure 9 ........................................................................ 14 changes to converter details section ......................................... 20 changes to internal/external reference section ....................... 21 changes to interface options section ......................................... 22 chang es to parallel interface section .......................................... 22 changes to serial interface (ser/ pa r sel = 1) section .......... 25 changes to daisy - chain mode (dcen = 1, ser/ pa r sel = 1) .. 27 changes to layout section ............................................................ 30 updated outline dimension ........................................................ 31 changes to ordering guide .......................................................... 31 7 /0 8 revision 0: initial version
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 3 of 32 specifications ad7656 - 1 v ref = 2.5 v internal/external, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v; f or the 4 v ref range, v dd = 10 v to 16.5 v, v ss = ?10 v to ?16.5 v ; f or the 2 v ref range, v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v; f sample = 250 ksps, t a = t min to t max , unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments dynamic performance f in = 10 khz sine wave signal -to - (noise + distortion) (sinad) 1 88 db signal -to - noise ratio (snr) 1 88 db total harmonic distortion (thd) 1 ? 90 db ?105 db v dd /v ss = 5 v to 16.5 v peak harmonic or spurious noise (sfdr) 1 ? 100 db intermodulation distortion (imd) 1 fa = 10.5 khz, fb = 9.5 khz second - order terms ?112 db third - order terms ? 107 db aperture delay 10 ns aperture delay matching 4 ns aperture jitter 35 ps channel - to - channel isolation 1 ? 100 db f in on unselected channels up to 100 khz full - power bandwidth 4.5 mhz @ ?3 db 2.2 mhz @ ?0.1 db dc accuracy resolution 16 bits no missing codes b version 15 bits y version 14 bits integral nonlinearity 1 3 lsb 1 lsb positive full - scale error 1 0.8 % fs r 0.381% fsr typical positive full - scale error matching 1 0.35 % fs r bipolar zero - scale error 1 0.0137% fsr typical b version 0.048 % fs r y version 0. 048 %f sr bipolar zero - scale error matching 1 0.038 % fs r negative full - scale error 1 0.8 % fs r 0.381% fsr typical negative full - scale error matching 1 0.35 % fs r analog input see table 8 for minimum v dd /v ss for each range input voltage ranges ? 4 v ref + 4 v ref v rngx bits or range pin = 0 ? 2 v ref + 2 v ref v rngx bits or range pin = 1 dc leakage current 1 a input capacitance 2 10 pf 4 v ref range when in track 14 pf 2 v ref range when in track reference input/outp ut reference input voltage range 2.5 2.5 v dc leakage current 1 a input capacitance 2 18.5 pf ref en/ dis = 1 reference output voltage 2.49 2.51 v long - term stability 150 ppm 10 00 hours reference temperature coefficient 25 ppm/c 6 ppm/c
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 4 of 32 parameter min typ max unit test conditions/comments logic inputs input high voltage (v inh ) 0.7 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in ) 10 a typically 10 na, v in = 0 v or v drive i nput capacitance (c in ) 2 10 pf logic outputs output high voltage (v oh ) v drive ? 0.2 v i source = 200 a output low voltage (v ol ) 0.2 v i sink = 200 a floating - state leakage current 10 a float ing - state output capacitance 2 10 pf output coding twos complement conversion rate conversion time 3.1 s track - and - hold acquisition time 1 , 2 550 ns throughput rate 250 ksps parallel interface mode only power requirements v dd ?5 + 16.5 v for the 4 v ref range, v dd = 10 v to 16.5 v v ss ?5 ?16.5 v for the 4 v ref range, v ss = ? 10 v to ?16.5 v av cc 4.75 5.25 v dv cc 4.75 5.25 v v drive 2.7 5.25 v i total 3 digital inputs = 0 v or v drive normal mode static 18 m a av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v normal mode operational 26 ma f sample = 250 ksps, av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v i ss (operational) 0.25 ma v ss = ?16.5 v, f sample = 250 ksps i dd (operat ional) 0.25 ma v dd = + 16.5 v, f sample = 250 ksps partial power - down mode 7 ma av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v full power - down mode ( stby pin) 60 a sclk on or off, av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v normal mode static 94 mw normal mode operational 140 mw f sample = 250 ksps partial power - down mode 40 mw full power - down mode ( stby pin) 315 w 1 see the terminology section. 2 sample tested during ini tial release to ensure compliance. 3 includes i av cc , i v dd , i v ss , i v drive , and i dv cc .
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 5 of 32 ad7657 - 1 v ref = 2.5 v internal/external, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v; f or the 4 v ref range, v dd = 10 v to 16.5 v, v ss = ?10 v to ?16.5 v; f or the 2 v ref range , v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v; f sample = 250 ksps, t a = t min to t max , unless otherwise noted. table 2 . parameter min typ max unit test conditions/comments dynamic performance f in = 10 khz sine wave signal -to - (noise + distortion) (sinad) 1 82.5 db signal -to - noise ratio (snr) 1 83.5 db total harmonic distortion (thd) 1 ? 90 db ?105 db peak harmonic or spurious noise (sfdr) 1 ? 100 db intermodulation distortion (imd) 1 fa = 10.5 khz, fb = 9.5 khz second - order terms ?109 db third - order terms ? 104 db aperture delay 10 ns aperture delay matching 4 ns aperture jitter 35 ps channel - to - channel isolation 1 ? 100 db f in on unselected channels up to 100 khz full - power bandwidth 4.5 mhz @ ?3 db 2.2 mhz @ ?0.1 db dc accuracy resolution 14 bits n o missing codes 14 bits integral nonlinearity 1 1 lsb 1 positive full - scale error 1 0.95 % fs r 0.27% fsr typical positive full - scale error matching 1 0.366 % fs r bipolar zero - scale error 1 0.04 % fs r 0.016% fsr typical bipolar zero - scale error matching 1 0.0427 % fs r negative full - scale error 1 0.95 % fs r 0.27% fsr typical negative full - scale error matching 1 0.366 % fs r analog input see table 8 for minimum v dd /v ss for each range input voltage ranges ? 4 v ref + 4 v ref v rngx bits or range pin = 0 ? 2 v ref + 2 v ref v rngx bits or range pin = 1 dc leakage current 1 a input capacitance 2 10 pf 4 v ref range when in track 14 pf 2 v ref range when in track reference input/output r eference input voltage range 2.5 2.5 v dc leakage current 1 a input capacitance 2 18.5 pf ref en/ dis = 1 reference output voltage 2.49 2.51 v long - term stability 150 ppm 1000 hours reference temperature coefficient 25 ppm/c 6 ppm/c logic inputs input high voltage (v inh ) 0.7 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in ) 10 a typically 10 na, v in = 0 v or v drive input capac itance (c in ) 2 10 pf
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 6 of 32 parameter min typ max unit test conditions/comments logic outputs output high voltage (v oh ) v drive ? 0.2 v i source = 200 a output low voltage (v ol ) 0.2 v i sink = 200 a floating - state leakage current 10 a floating - state output capacitance 2 10 pf output coding twos complement conversion rate conversion time 3.1 s track - and - hold acquisition time 1 , 2 550 ns throughput rate 250 ksps parallel interface mode only power requirements v dd ?5 + 16.5 v for the 4 v ref range, v dd = 10 v to 16.5 v v ss ?5 ?16.5 v for the 4 v ref range, v ss = ?10 v to ?16.5 v av cc 4.75 5.25 v dv cc 4.75 5.25 v v drive 2.7 5.25 v i total 3 digital inputs = 0 v or v drive normal mode static 18 ma av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v normal mode operational 26 ma f sample = 250 ksps, av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v i ss (operational) 0.25 ma v ss = ?16.5 v, f sample = 250 ksps i dd (oper ational) 0.25 ma v dd = 16.5 v, f sample = 250 ksps partial power - down mode 7 ma av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v full power - down mode ( stby pin) 60 a sclk on or off, av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v normal mode static 94 mw normal mode operational 140 mw f sample = 250 ksps partial power - down mode 40 mw full power - down mod e ( stby pin) 315 w 1 see the terminology section. 2 sample tested during initial release to ensure compliance. 3 includes i av cc , i v dd , i v ss , i v drive , and i dv cc .
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 7 of 32 ad7658 - 1 v ref = 2.5 v internal/external, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v; f or 4 v ref range, v dd = 10 v to 16.5 v, v ss = ?10 v to ?16.5 v; f or 2 v ref range , v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v; f sample = 250 ksps, t a = t min to t max , unless otherwise noted. table 3 . parameter min typ max unit test conditions/comments dynamic performance f in = 10 khz sine wave signal -to - (nois e + distortion) (sinad) 1 73.5 db 73.5 db total harmonic distortion (thd) 1 ? 88 db ?100 db peak harmonic or spurious noise (sfdr) 1 ? 97 db intermodulation distortion (i md) 1 fa = 10.5 khz, fb = 9.5 khz second - order terms ?106 db third - order terms ? 101 db aperture delay 10 ns aperture delay matching 4 ns aperture jitter 35 ps channel - to - channel isolation 1 ? 100 db f in on unselected channels up to 100 khz full - power bandwidth 4.5 mhz @ ?3 db 2.2 mhz @ ?0.1 db dc accuracy resolution 12 bits no missing codes 12 bits differential nonlinearity 0.7 ls b integral nonlinearity 1 0.5 lsb positive full - scale error 1 0.95 % fs r 0.317% fsr typical positive full - scale error matching 1 0.366 % fs r b ipolar zero - scale error 1 2 lsb 0.0125% fsr typical bipolar zero - scale error matching 1 2 lsb negative full - scale error 1 0.95 % fs r 0.317% fsr typ ical negative full - scale error matching 1 0.366 % fs r analog input see table 8 for minimum v dd /v ss for each range input voltage ranges ? 4 v ref + 4 v ref v rngx bits or range pin = 0 ? 2 v ref + 2 v ref v rngx bits or range pin = 1 dc leakage current 1 a input capacitance 2 10 4 v ref range when in track 14 pf 2 v ref range when in track reference input/output reference input voltage range 2.5 2.5 v d c leakage current 1 a input capacitance 2 18.5 pf ref en/ dis = 1 reference output voltage 2.49 2.51 v long - term stability 150 ppm 1000 hours reference temperature coefficient 25 ppm/ c 6 ppm/c logic inputs input high voltage (v inh ) 0.7 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in ) 10 a typically 10 na, v in = 0 v or v drive input capacitance (c in ) 2 10 pf
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 8 of 32 parameter min typ max unit test conditions/comments logic outputs output high voltage (v oh ) v drive ? 0.2 v i source = 200 a output low voltage (v ol ) 0.2 v i sink = 200 a floating - state leakage current 10 a floating - state output capacitance 2 10 pf output coding twos complement conversion rate conversion time 3.1 s track - and - hold acquisition time 1 , 2 550 ns throughput rate 250 ksps paral lel interface mode only power requirements v dd ? 5 + 16.5 v for the 4 v ref range, v dd = 10 v to 16.5 v v ss ?5 ?16.5 v for the 4 v ref range, v ss = ?10 v to ?16.5 v av cc 4.75 5.25 v dv cc 4.75 5.25 v v drive 2.7 5.25 v i total 3 digital inputs = 0 v or v drive normal mode static 18 ma av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss =?16.5 v normal mode operational 26 ma f sample = 250 ksps, av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ? 16.5 v i ss (operational) 0.25 ma v ss = ?16.5 v, f sample = 250 ksps i dd (operat ional) 0.25 ma v dd = 16.5 v, f sample = 250 ksps partial power - down mode 7 ma av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v full power - down mode ( stby pin) 60 a sclk on or off, av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = + 5.25 v, v dd = + 16.5 v, v ss = ?16.5 v normal mode static 94 mw normal mode operational 140 mw f sample = 250 ksps partial power - down mode 40 mw full power - down mode ( stby pin) 315 w 1 see the terminology section. 2 sample tested during initial release to ensure compliance. 3 includes i av cc , i v dd , i v ss , i v drive , and i dv cc .
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 9 of 32 timing specification s av cc and dv cc = 4.75 v to 5.25 v, v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v internal/external, t a = t min to t max , unless otherwise noted. table 4 . parameter 1 limit at t min, t max unit description v drive < 4.75 v v drive = 4.75 v to 5.25 v parallel interface t convert 3 3 s typ conversion time, internal clock t quiet 150 150 ns min minimum quiet time required be tween bus relinquish and start of next conversion t acq 550 550 ns min acquisition time t 10 25 25 ns min minimum convst low pulse t 1 60 60 ns max convst high to busy high t wake - up 2 2 ms max stby rising edge to convst rising edg e 25 25 s max partial power - down mode parallel read operation t 2 0 0 ns min busy to rd delay t 3 0 0 ns min cs to rd setup time t 4 0 0 ns min cs to rd hol d time t 5 45 36 ns min rd pulse width t 6 45 36 ns max data access time after rd falling edge t 7 10 10 ns min data hold time after rd rising edge t 8 12 12 ns max bus relinquish time after rd rising edge t 9 6 6 ns min minimum time between reads parallel write operation t 11 15 15 ns min wr pulse width t 12 0 0 ns min cs to wr setup time t 13 5 5 ns min cs to wr hold time t 14 5 5 ns min data setup time before wr rising edge t 15 5 5 ns min data hold after wr rising edge serial interface f sclk 18 18 mhz max frequency of serial read clock t 16 12 12 ns max delay from cs until dout x three - state disabled t 17 2 22 22 ns max data access time after sclk rising edge/ cs falling edge t 18 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 19 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 20 10 10 ns min sclk to data valid hold time after sclk falling edge t 21 18 18 ns max cs rising edge to dout x high impedance 1 sample tested during initial release to ensure compliance. all input signals are speci fied with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 a buffer i s used o n the doutx pins (pin 5 to pin 7) for thi s measurement. 200a i ol 200a i oh 1.6v t o output pin c l 25pf 07017-002 figure 2 . load circuit for digital output timing specification s
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 10 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5 . parameter rating v dd to agnd, dgnd ?0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to ?16.5 v v dd to av cc v cc ? 0.3 v to + 16.5 v av cc to agnd, dgnd ?0.3 v to +7 v dv cc to av cc ?0.3 v to av cc + 0.3 v dv cc to dgnd, agnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v v drive to dgnd ?0.3 v to dv cc + 0.3 v analog input voltage to agnd 1 v ss ? 0.3 v to v dd + 0.3 v digital input voltage t o dgnd ?0.3 v to v drive + 0.3 v digital output voltage to d gnd ?0.3 v to v drive + 0.3 v refin/refout to agnd ?0.3 v to av cc + 0.3 v input current to any pin except supplies 2 10 ma operating temperature range b version ?40c to +85c y version ?40 c to +125c storage temperature range ?65c to +150c junction temperature 150c pb/ sn temperature, soldering reflow (10 sec to 30 sec) 240(+0)c pb - free temperature, soldering reflow 260(+0)c esd 1.5 k v 1 if the analog inputs are driven from al ternative v dd and v ss supply circuitry, a 240 ? series resistor should be placed on the analog inputs and schottky diodes should be placed in series with the v dd and v ss supplies o f the ad7656 - 1/ad7657 - 1/ad7658 - 1 . 2 transient currents of up to 100 ma do n ot cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the oper ational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. these specifications apply to a 4 - layer board. table 6 . thermal resistance package type ja jc unit 64- lead lqfp 45 11 c/w esd caution
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 11 of 32 pin configuration an d function descripti ons 64 db15 63 wr/ref en/dis 62 h/s se l 61 ser/ p ar se l 60 a v cc 59 agnd 58 refcapc 57 agnd 56 refcapb 55 agnd 54 refca p a 53 agnd 52 agnd 51 refin/refout 50 a v cc 49 agnd 47 a v cc 46 a v cc 45 v5 42 v4 43 agnd 44 agnd 48 v6 41 a v cc 40 a v cc 39 v3 37 agnd 36 v2 35 a v cc 34 a v cc 33 v1 38 agnd 2 db13 3 db12 4 db 1 1 7 db8/dout a 6 db9/dout b 5 db10/dout c 1 db14/refbuf en/dis 8 dgnd 9 v drive 10 db7/hben/dcen 12 db5/dcin a 13 db4/dcin b 14 db3/dcin c 15 db2/se l c 16 db1/se l b 1 1 db6/sclk 17 db0/se l a 18 bus y 19 cs 20 rd 21 convst c 22 convst b 23 convst a 24 stb y 25 dgnd 26 dv cc 27 range 28 reset 29 w/b 30 v ss 31 v dd 32 agnd pin 1 ad7656-1/ad7657-1/ad7658-1 top view (not to scale) 07017-003 figure 3 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 54, 56, 58 refcapa, refcapb, r efcapc reference capacitor a, reference capacitor b, and reference capacitor c. decoupling capacitors are connected to these pins to decouple the reference buffer for each adc pair. decouple e ach refcap pin to agnd using a 1 f capacitor . 33, 36, 39, 42, 45, 48 v1 to v6 analog input 1 to analog input 6. these pins are single - ended analog inputs. in hardware mode, the analog input range o f these channels is determined by the range pin. in software mode, it is determined by the rngc to rnga bits of the cont rol register (see table 11 ). 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 agnd analog ground. this pin is the g round reference point for all analog circuitry on the ad7656 - 1/ ad7657 - 1/ad7658-1. refer a ll analog input signals and e xternal reference signal s to this pin . connect a ll agnd pins to the agnd plane of the system. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 26 dv cc digital power, 4.75 v to 5.25 v. the dv cc and av cc voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. decouple t his supply to dgnd by placing a 1 f decoupling capacitor on the dv cc pin. 9 v drive logic power sup ply input. the voltage supplied at this pin determines the operating voltage of the interface. this pin is n ominally at the same supply as the supply of the host interface. 8, 25 dgnd digital ground. this is the ground reference point for all digital cir cuitry on the ad7656 - 1/ad7657 - 1/ ad7658 - 1. connect b oth dgnd pins to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 34, 35, 40, 41, 46, 47, 5 0, 60 av cc analog supply voltage, 4.75 v to 5.25 v. this is the supply voltage for the adc cores. the av cc and dv cc voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 21, 22, 23 convst c , co nvst b, convst a conversion start input a, conversion start input b, and conversion start input c. these logic inputs are used to initiate conversions on the adc pairs. convst a is used to initiate simultaneous conversions on v1 and v2. convst b is used to initiate simultaneous conversions on v3 and v4. convst c is used to initiate simultaneous conversions on v5 and v6. when one of these pins switches from low to high, the track - and - hold switch on the selected adc pair switches from track to hold , and the c onversion is initiated. these inputs can also be used to place the adc pairs into partial power - down mode.
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 12 of 32 pin no. mnemonic description 19 cs chip select. this active low logic input frames the data transfer. if both cs and rd ar e logic low and the parallel interface is selected , the output bus is enabled and the conversion result is output on the parallel data bus lines. if both cs and wr are logic low and the parallel interface is selected , db [15:8] are used to write data to the on - chip control register. when the serial interface is selected , the cs is used to frame the serial read transfer and clock out the msb of the serial output data. 20 rd read data. if both cs and rd are logic low and the parallel interface is selected , the output bus is enabled. when the serial interface is selected , the rd line should be held low. 63 wr /ref en/ dis write data/reference enable and disable . when the h /s sel pin is high and both cs and wr are logic low, db[15:8] are used to write data to the internal control register. when the h /s sel pin is low, this pin is used to enable or disable the internal reference. when h /s sel = 0 and ref en/ dis = 0, the internal reference is disabled and an external reference should be applied to the r efin/refout pin. when h /s sel = 0 and ref en/ dis = 1, the internal reference is enabled and the refin/refout pin should be decoupled. see the internal/external reference section . 18 busy busy output. this pin transitions to high when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. a new conversion can not be initiated on the ad7656 - 1/ad7657 - 1/ad7658 - 1 w hen the busy signal is high because any applied convst edges are ignored . 51 refin/refout reference input/ reference output. the on - chip reference is available via this pin . alternatively, the internal reference can be disabled and an external reference ca n be applied to this input. see the internal/external reference section . when the internal reference is enabled, decouple this pin using at least a 1 f decoupling cap acitor . 61 ser/ par sel serial/ parallel se lection input. when this pin is low, the parallel interface is selected. when this pin is high, the serial interface is selected. when the serial interface is selected , db[10:8] function as dout[c:a], db[0:2] function as dout, and db7 functions as dcen. wh en the serial interface is selected , tie db15 and db[13:11] to dgnd. 17 db0/sel a data bit 0/select dout a. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1, this pi n functions as sel a and is used to configure the serial interface. if this pin is 1, the ser ial interface operates with one, two, or three dout output pins and enables dout a as a serial output. when the serial interface is selected , always set this pin t o 1. 16 db1/sel b data bit 1/select dout b. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1, this pin functions as sel b and is used to configure the serial interfa ce. if this pin is 1, the serial interfac e operates with two or three dout output pins and enables dout b as a serial output. if this pin is 0, the dout b is not enabled to operate as a serial data output pin and only one dout output pin, dout a, is used. unused serial dout pins should be left unconnected. 15 db2/sel c data bit 2/select dout c. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1, this pin functions as s el c and is used to configure the serial interface. if this pin is 1, the serial interface operates with three dout output pins and enables dout c as a serial output. if this pin is 0, the dout c is not enabled to operate as a serial data output pin. unuse d serial dout pins should be left unconnected. 14 db3/dcin c data bit 3/daisy - chain input c. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1 and dcen = 1, this pin acts as daisy - chain input c. when the serial interface is selected but the device is not used in daisy - chain mode, tie this pin to dgnd. 13 db4/dcin b data bit 4/daisy - chain input b. when ser/ par sel = 0, this pin acts as a three - state p arallel digital output pin. when ser/ par sel = 1 and dcen = 1, this pin acts as daisy - chain input b. when the serial interface is selected but the device is not used in daisy - chain mode, tie this pin to dgnd. 12 db5/dcin a data bit 5/dai sy - chain input a. when ser/ par sel is low, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1 and dcen = 1, this pin acts as daisy - chain input a. when the serial interface is selected but th e device is not used in daisy - chain mode, tie this pin to dgnd. 11 db6/sclk data bit 6/serial clock. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1, this pin funct ions as sclk input and is the read serial clock for the serial transfer. 10 db7/hben/dcen data bit 7/high byte enable/daisy - chain enable. when the parallel interface is selected and the device is used in word mode (ser/ par sel = 0 and w /b = 0), this pin functions as data bit 7. when the parallel interface is selected and the device is used in byte mode (ser/ par sel = 0 and w /b = 1), this pin functions as hben. if the hben pin is logic high, the data is output msb byte first on db[15:8]. if the hben pin is logic low, the data is output lsb byte first on db[15:8]. when the serial interface is selected (ser/ par sel = 1), this pin functions as dcen. if the dcen pin is logi c high, the parts operate in daisy - chain mode with db[5:3] functioning as dcin[a:c]. when the serial interface is selected but the device is not used in daisy - chain mode, this pin should be tied to dgnd.
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 13 of 32 pin no. mnemonic description 7 db8/dout a data bit 8/serial data output a. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1 and sel a = 1, this pin functions as dout a and outputs serial conversion data. 6 db9/dout b data bit 9/serial data outpu t b. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1 and sel b = 1, this pin functions as dout b and outputs serial conversion data. this configures the serial inter face to have two dout output lines. 5 db10/dout c data bit 10/serial data output c. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1 and sel c = 1, this pin function s as dout c and outputs serial conversion data. this configures the serial interface to have three dout output lines. 4 db11 data bit 11/digital ground. when ser/ par sel = 0, this pin acts as a three - state parallel digital output pin. wh en ser/ par sel = 1, tie this pin to dgnd. 2, 3 , 64 db13, db12, db15 data bit 12, data bit 13, data bit 15. when ser/ par sel = 0, these pins act as three - state parallel digital input/output pins. when cs and rd are low, these pins are used to output the conversion result. when cs and wr are low, these pins are used to write to the control register. when ser/ par sel = 1, tie these pin s to dgnd. for the ad7657 -1 , db15 contains a leading 0 . for the ad7658 -1 , db15, db13, and db12 contain leading 0 s. 1 db14/refbuf en /dis data bit 14/reference buffer enable and disable. when ser/ par sel = 0, this pin acts as a three - state digital input/ output pin. for the ad7657 -1 and ad7658 - 1 , db14 contains a leading 0 . when ser/ par sel = 1, this pin can be used to enable or disable the internal reference buffers. 28 reset reset input. when set to logi c high, this pin resets the ad7656 - 1/ad7657- 1/ad7658- 1. in software mode , the current conversion is aborted and the internal register is set to all 0s. in hardware mode, the ad7656 - 1/ad7657- 1/ad7658- 1 are configured depending on the logic levels on the har dware select pins. in all modes, the parts should receive a reset pulse after power - up. the reset high pulse should be typically 100 ns wide. the convst pin may be held high during the reset pulse. however, if the convst pin is held low during the reset pu lse, then a fter the reset pulse, the ad7656 - 1/ad7657-1 /ad7658 - 1 need to receive a complete convst pulse to initiate the first conversion; this should consist of a high - to - low convst edge followed by a low - to - high convst edge. in hardware mode , the user ca n initiate a reset pulse between conversion cycles, that is, a 100 ns reset pulse can be applied to the device after busy ha s transitioned from high to low and the data has be en read. the reset can then be is s u ed prior to the next complete convst pulse. en s ure that in such a case , reset has returned to logic low prior to the next complete convst pulse. 27 range analog input range selection. logic input. the logic level on this pin determines the input range of the analog input channels. when this pin is l ogic 1 at the falling edge of busy, the range for the next conversion is 2 v ref . when this pin is logic 0 at the falling edge of busy, the range for the next conversion is 4 v ref . in hardware select mode, the range pin is checked on the falling edge of busy. in software mode ( h /s sel = 1), the range pin can be tied to dgnd , and the input range is determined by the rnga, rngb, and rngc bits in the control register. 31 v dd positive power supply voltage. this is the positive supply vo ltage for the analog input section. 30 v ss negative power supply voltage. this is the negative supply voltage for the analog input section . 24 stby standby mode input. this pin is used to put all six on - chip adcs into standby mode. the stby pin is high for normal operation and low for standby operation. 62 h /s sel hardware /software select input. logic input. when h /s sel = 0, the ad7656 - 1/ad7657 - 1/ad7658 - 1 operate in hardware select mode, and the adc pairs to be simultaneously sampled are selected by the convst pins. when h /s sel = 1, the adc pairs to be sampled simultaneously are selected by writing to the control register. when the serial interfa ce is selected , convst a is used to initiate conversions on the selected adc pairs. 29 w /b word /byte input. when this pin is logic low, data can be transferred to and from the ad7656 -1/ ad7657 - 1/ad7658- 1 using the parallel data lines db[ 15:0]. when this pin is logic high and the parallel interface is selected , byte mode is enabled. in this mode, data is transferred using data lines db[15:8] , and db 7 function s as hben. to obtain the 16- bit conversion result, 2 - byte reads are required. whe n the serial interface is selected , tie this pin to dgnd.
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 14 of 32 typical performance characteristics 0 ?160 ?180 frequency (khz) amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 07017-004 40 60 80 100 120 20 0 v dd /v ss = 15v av cc /dv cc /v drive = 5v 10v range internal reference t a = 25c f sample = 250ksps f in = 10khz snr = 88.44db sinad = 88.43db thd = ?111.66db figure 4 . ad7656- 1 fft for 5 v range (v dd /v ss = 15 v) 0 ?160 ?180 frequency (khz) amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 07017-005 40 60 80 100 120 20 0 v dd /v ss = 12v av cc /dv cc /v drive = 5v 5v range internal reference t a = 25c f sample = 250ksps f in = 10khz snr = 88.25db sinad = 88.24db thd = ?112.46db figure 5 . ad7656- 1 fft for 5 v range (v dd /v ss = 12 v) 2.0 ?2.0 0 10k 20k 30k 40k 50k 60k 65535 code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 07017-006 v dd /v ss = 12v av cc /dv cc /v drive = 5v f sample = 250ksps 2 v ref range t a = ?40c inl wcp = 0.97lsb inl wcn = ?0.72lsb figure 6 . ad7656- 1 typical inl 2.0 ?2.0 0 10k 20k 30k 40k 50k 60k 65535 code dnl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 07017-007 v dd /v ss = 12v av cc /dv cc /v drive = 5v f sample = 250ksps 2 v ref range t a = ?40c dnl wcp = 0.61lsb dnl wcn = ?0.82lsb figure 7 . ad7656 - 1 typical dnl 2.0 ?2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 inl (lsb) code v dd /v ss = 12v av cc /dv cc /v drive = 5v f sample = 250ksps 5v range 07017-008 1.6 1.2 0.8 0.4 0 ?0.4 ?0.8 ?1.2 ?1.6 figure 8 . ad7657 - 1 typical inl 2.0 ?2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 dnl (lsb) code 07017-009 v dd /v ss = 12v av cc /dv cc /v drive = 5v f sample = 250ksps 5v range figure 9 . ad7657 - 1 typical dnl
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 15 of 32 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 inl (lsb) code 07017-010 v dd /v ss = 12v av cc /dv cc /v drive = 5v f sample = 250ksps 5v range fig ure 10 . ad7658 - 1 typical inl 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 dnl (lsb) code v dd /v ss = 12v av cc /dv cc /v drive = 5v f sample = 250ksps 5v range 07017-011 figure 11 . ad7658 - 1 typical dnl 90 83 10 100 07017-012 analog input frequency (khz) sinad (db) 89 88 87 86 85 84 f sample = 250ksps t a = 25c internal reference 10v range v dd /v ss = 12v av cc /dv cc /v drive = 5v 5v range v dd /v ss = 12v av cc /dv cc /v drive = 5v figure 12 . ad7656 - 1 sinad vs. analog input frequency ?80 ?1 15 10 100 07017-013 analog input frequency (khz) thd (db) ?85 ?90 ?95 ?100 ?105 ?110 f sample = 250ksps t a = 25c internal reference 10v range v dd /v ss = 12v av cc /dv cc /v drive = 5v 5v range v dd /v ss = 12v av cc /dv cc /v drive = 5v figure 13 . ad7656 - 1 thd vs. an alog input frequency ?80 ?120 10 100 07017-014 analog input frequency (khz) thd (db) ?90 ?100 ?110 v dd /v ss = 16.5v av cc /dv cc /v drive = 5.25v t a = 25c internal reference 4 v ref range r source = 1000? r source = 220? r source = 50? r source = 100? r source = 10? figure 14 . ad7656 - 1 thd vs. analog input frequency for various source impedances, 4 v ref range ?80 ?1 15 10 100 07017-015 analog input frequency (khz) thd (db) ?85 ?90 ?95 ?100 ?105 ?110 v dd /v ss = 12v av cc /dv cc /v drive = 5v t a = 25c internal reference 2 v ref range r source = 1000? r source = 220? r source = 100? r source = 50? r source = 10? figure 15 . ad7656 - 1 thd vs. analog input frequency for various source impedance s, 2 v ref range
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 16 of 32 ?55 125 temperature (c) reference voltage (v) ?35 ?15 5 25 45 65 85 105 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 av cc /dv cc /v drive = 5v v dd /v ss = 12v 07017-016 figure 16 . reference voltage vs. temperature 3.20 2.70 ?55 125 temperature (c) conversion time (s) 3.15 3.10 3.05 3.00 2.95 2.90 2.85 2.80 2.75 ?35 ?15 5 25 45 65 85 105 av cc /dv cc /v drive = 5v v dd /v ss = 12v 07017-017 figure 17 . conversion time vs. temperature 3500 ?5 code number of occurrences 3 3000 2500 2000 1500 1000 500 ?4 ?3 ?2 ?1 0 1 2 v dd /v ss = 15v av cc /dv cc /v drive = 5v internal reference 8192 samples 25 168 1532 3212 2806 392 57 0 0 0 07017-018 figure 18 . ad7656 - 1 histogram of codes 100 40 30 530 supply ripple frequency (khz) psrr (db) 90 80 70 60 50 80 130 180 230 280 330 380 430 480 v dd v ss f sample = 250ksps 2 v ref range internal reference t a = 25c f in = 10khz 100nf on v dd and v ss 07017-019 figure 19 . psrr vs. supply ripple frequency 90 85 ?40 140 07017-020 temperature (c) snr (db) 89 88 87 86 ?20 0 20 40 60 80 100 120 10v range av cc /dv cc /v drive = 5.25v v dd /v ss = 16.5v 5v range av cc /dv cc /v drive = 5v v dd /v ss = 12v f sample = 250ksps f in = 10khz internal reference figure 20 . ad7656 - 1 snr vs. temperature ?90 ?120 ?60 140 07017-021 temperature (c) thd (db) ?95 ?100 ?105 ?110 ?115 ?40 ?20 0 40 20 60 80 100 120 10v range av cc /dv cc /v drive = 5.25v v dd /v ss = 16.5v 5v range av cc /dv cc /v drive = 5v v dd /v ss = 12v f sample = 250ksps f in = 10khz internal reference figure 21 . ad7656 - 1 thd vs. temperature
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 17 of 32 120 60 0 frequency of input noise (khz) channel-to-channel isolation (db) av cc /dv cc /v drive = 5v v dd /v ss = 12v t a = 25c internal reference 2 v ref range 30khz on selected channel 110 100 90 80 70 20 40 60 80 100 120 140 07017-022 figure 22 . channel - to - channel isolation vs. frequency of input noise 10 12 14 16 18 20 22 ?40 ?20 0 20 40 60 80 100 120 temperature (c) dynamic current (ma) 5v range 10v range av cc /dv cc /v drive = 5v f sample = 250ksps for 5v range v dd /v ss = 12v for 10v range v dd /v ss = 16.5v 07017-023 figure 23 . dynamic current vs. temperature 95 60 30 07017-036 supply ripple frequency (khz) psrr (db) 90 85 80 75 70 65 70 110 150 190 230 f sample = 250ksps 2 v ref range internal reference t a = 25c f in = 10khz 1f on av cc supply pin 100mv supply ripple amplitude figure 24 . psrr vs. supply ripple frequency for av cc supply
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 18 of 32 terminology integral nonlinearity (inl) the maximum deviati on from a straight line passing through the endpoints of the adc transfer function. the endpoints of the t ransfer function are zero scale at a ? lsb below the first code transition and full scale at ? lsb above the last code transition. differential nonli nearity (dnl) the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero scale error the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, that is, agnd ? 1 lsb. bipolar zero scale error matching the difference in bipolar zero code error between any two input channels. positive full - scale error the deviation of the last code transition (011 110 to 011 111) from the ideal (+4 v ref ? 1 lsb, +2 v ref ? 1 lsb) after adjusting for the bipolar zero scale error. positive full - scale error match ing the difference in positive full - scale error between any two input channels. negative full - scale error the deviation of the first code tr ansition (10 000 to 10 001) from the ideal (?4 v ref + 1 lsb, ?2 v ref + 1 lsb) after adjusting for the bipolar zero scale error. negative full - scale error match ing the difference in negative full - scale error between any two input channels. track - and - hold acquisition time the track - and - hold amplifier returns to track mode at the end of the conversion. the track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 1 lsb, after t he end of the conversion. see the track - and - hold section for more details. signal -to -( noise + distortion ) ratio (sinad) the measured ratio of signal - to - (noise + distortion ) at the output of the adc. the signal is the rms amplitud e of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s ample /2, excluding dc). the ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantiza tion noise. the theoretical sinad ratio for an ideal n - bit converter with a sine wave input is given by sinad = (6.02 n + 1.76) db therefore, sinad is 98 db for a 16 - bit converter, 86.04 db for a 14- bit converter, and 74 db for a 12 - bit converter. tot al harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. for the ad7656 - 1/ad7657 - 1/ad7658 - 1, it is defined as 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 ) db ( + + + + = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms ampl itudes of the second through sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s ample /2, excluding dc) to the rms value of the fundamental. normally, the value of t his specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion (imd) with inputs consisting of sine waves at two frequenc ies, fa and fb, any active device with nonlinearities create distortion products at the sum and difference frequencies of mfa nfb, where m , n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7656 - 1/ad7657 - 1/ad7658 - 1 are tested using the ccif standard in which two input frequencies near the maximum input bandwidth are used. in this case, the second - order terms are usually distanced in frequency from the original sine waves, and the third - order terms are usually at a frequency close to the input frequencies. as a result, the second - and third - order t erms are specified separately. the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals and is expressed i n decibels. channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full - scale, 100 khz sine wave signal to all unselected input channels and determining the de gree to which the signal attenuates in the selected channel with a 30 khz signal. power supply rejection (psr) variations in power supply affect the full - scale transition but not the linearity of the converter . power supply rejection is the maximum change in the full - scale transition point due to a change in power supply voltage from the nominal value. see the typical performance characteristics section.
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 19 of 32 figure 19 shows the power supply rejection rati o vs. supply ripple frequency for the ad7656 - 1/ad7657 - 1/ad7658 - 1. the power supply rejection ratio is defined as the ratio of the power in the adc output at full - scale frequency, f, to the power of a 200 m v p - p sine wave applied to the v dd and v ss supplies of the adc at a frequency sampled, f s ample , as follows: psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at f requency f in the adc output. pf s is equal to the power at f requency f s ample coupled onto the v dd and v ss supplies. % fsr %fsr is calc ulated using the full theoretical span of the adc.
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 20 of 32 theory of operation converter details the ad7656 - 1/ad7657 - 1/ad7658 - 1 ar e pin - and software - compatible, reduced decoupling versions of the ad7656/ad7657/ ad7658 devices. in addition, t he ad7656 - 1/ad7657 - 1/ad7658 - 1 are high speed, low power converters that allow the simultaneous sampling of six on - chip adcs. the analog inp uts on the ad7656 - 1/ ad7657 - 1/ ad7658 - 1 can accept true bipolar input signals. the range pin or rng x bits are used to select either 4 v ref or 2 v ref as the input range for the next conversion. each ad7656 - 1/ad7657 - 1/ad7658 - 1 contain s six sar adcs, si x track - and - hold amplifiers, an on - chip 2.5 v reference, reference buffers, and high speed parallel and serial interfaces. the parts allow the simultaneous sampling of all six adcs when the three convst pins (convst a, convst b, and convst c) are tied toge ther. alternatively, the six adcs can be grouped into three pairs. each pair has an associated convst signal used to initiate simultaneous sampling on each adc pair, on four adcs, or on all six adcs. convst a is used to initiate simultaneous sampling on v1 and v2, convst b is used to initiate simul - taneous sampling on v3 and v4, and convst c is used to initiate simultaneous sampling on v5 and v6. a conversion is initiated on the ad7656 - 1/ad7657 - 1/ad7658 - 1 by pulsing the convst input. on the rising edge of c on vst, the track - and - hold amplifier of the selected adc pair is placed into hold mode and the conversions are started. after the rising edge of convst, the busy signal goes high to indicate that the conversion is taking place. the conversion clock for the ad7656 - 1/ ad7657 - 1/ad7658 - 1 is internally generated, and the conversion time for the parts is 3 s. any further convst rising edges on either convst a, convst b or convst c are ignored as long as busy is high. the busy signal returns low to indicate the e nd of a conversion. on the falling edge of busy, the track - and - hold amplifier returns to track mode. data can be read from the output register via the parallel or serial interface. track - and - hold amplifiers the track - and - hold amplifiers on the ad7656 - 1/ad7 657 - 1/ ad7658 - 1 allow the adcs to accurately convert an input sine wave of full - scale amplitude to 16 - /14 - /12 - bit resolution , respectively. the input bandwidth of the track - and - hold amplifiers is greater than the nyquist rate of the adc, ev en when the ad7 656- 1/ ad7657 - 1/ad7658 - 1 are operating at the maximum throughput rate. the parts can hand le input frequencies of up to 4.5 mhz. the track - and - hold amplifiers sample their respective inputs simultaneous ly on the rising edge of convst . the aperture time (that is, the delay time between the external convst signal actually going into hold) for the track - and - hold amplifier is 10 ns. this is well matched across all six track - and - hold amplifier s on one device and from device to device. this allows more than six adc s to be sampled simultaneously. the end of the conversion is signaled by the falling edge of busy, and it is at this point that the track - and - hold amplifier s return to track mode and the acquisition time begins. analog input the ad7656 - 1/ad7657 - 1/ad7658 - 1 can handle true bipolar input voltages. the logic level on the range pin or the value written to the rngx bits in the control register determines the analog input range on the ad7656 - 1/ad7657 - 1/ad7658 - 1 for the next conversion. when the range pin or rngx b it s are 1, the analog input range for the next conversion is 2 v ref . when the range pin or rngx bit s are 0, the analog input range for the next conversion is 4 v ref . d1 d2 v dd c2 r1 v1 v ss c1 07017-024 figure 25 . equivalent analog input structure figure 25 shows an equivalent circuit of the analog input structure of the ad7656 - 1/ad7657 - 1/ad7658 - 1. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never e xceeds the v dd and v ss supply rails by more than 300 mv. signals exceeding this value cause these diodes to become forward - biased and to start conducting current into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the parts is 10 ma. capacitor c1 in figure 25 is typically about 4 pf and can be attributed primarily to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch ( that is, a track - and - hold switch). this resistor is typically about 3.5 k ?. capacitor c2 is the adc sampling capacitor and has a capacitance of 10 pf typically. the ad7656 - 1/ad7657 - 1/ad7658 - 1 require v dd and v ss dual supplies for the high voltage analog input structures. these supplies must be equal to or greater than the anal og input range (see table 8 for the requirements on these supplies for each analog input range). the ad7656 - 1/ad7657 - 1/ad7658 - 1 require a low voltage av cc supply of 4.75 v to 5.25 v to power the adc core, a dv cc supply of 4.75 v to 5.25 v for the digital power, and a v drive supply of 2.7 v to 5.25 v for the interface power. to meet the specified performance when using the minimum supply voltage for the selected analog input range, it may be necessary to reduce the throughput rate from the maximum throughput rate. table 8 . minimum v dd /v ss supply voltage requirements analog input range (v) reference voltage (v) full - scale input (v) minimum v dd /v ss (v) 4 v ref 2.5 10 10 2 v ref 2.5 5 5
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 21 of 32 adc transfer function the output coding of the ad7656 - 1/ad7657 - 1/ad7658 - 1 is twos complement. the designed code transitions occur midway between successive integer lsb values, that is, 1?2 lsb, 3?2 lsb. the lsb size is fsr/65,536 for the ad7656 - 1, fsr/16 , 384 for the ad7657 - 1, and fsr/4096 for the ad7658 - 1. the ideal transfer characteristic is shown in figure 26. 01 1 ... 11 1 01 1 ... 1 10 000 ... 001 000 ... 000 11 1 ... 11 1 ?fsr/2 + 1/2lsb +fsr/2 ? 3/2lsb agnd ? 1lsb analog input adc code 100 ... 010 100 ... 001 100 ... 000 07017-025 figure 26 . ad7656 - 1/ad 7657 - 1/ad7658 - 1 transfer characteristic the lsb size is dependent on the analog input range selected (see table 9 ). internal/external reference the r e fin/refout pin allows access to the 2.5 v reference of the ad7656 - 1 / ad7657 - 1 / ad7 658 - 1, or it allows an external reference to be connected to provide the reference source for conversions. the ad7656 - 1/ad7657 - 1/ad7658 - 1 can each accommodate a 2.5 v external reference . when applyi ng an external reference via the refin/refout pin , the in ternal reference must be disabled and the reference buffers must be enabled . alternatively, an external refernce can be applied via the refcapx pins, in which case the internal reference should be disabled and it is recommended to disable the reference b uffers to save power and minimize crosstalk. after a reset, the ad7656 - 1/ ad7657 - 1/ad7658 - 1 default to operating in external reference mode with the internal reference disabled and the reference buffers enabled. the internal reference can be enabled in eit her hardware or software mode. to enable the internal reference in hardware mode, set the h /s sel pin to 0 and the ref en/ dis pin to 1. to enable the internal reference in software mode, set h /s sel to 1 and write to the control register to set db9 of the register to 1. for the internal reference mode, decouple the refin/refout pin using a 1 f capacitor. the ad7656 - 1/ad7657 - 1/ad7658 - 1 each contain three on - chip reference buffers as shown in figure 27 . each of the three adc pairs has an associated reference buffer. these reference buffers require external decoupling capacitors , using 1 f capacitors, on the refcapa, refcapb, and refcapc pins. the internal reference buffers can be disabled in software mode by writing to bit db8 in the internal control register. if a serial interface is selected , the internal reference buffers can be disabled in hardware mode by setting the db14/refbuf en / dis pin high. if the intern al reference and its buffers are disabled, apply an external buffered reference to the refcap x pins. buf sar ref sar buf sar sar buf sar sar refcapa refin/ refout refcapb refcapc 07017-127 figure 27 . reference circuit typical connection d iagram figure 28 shows the typical connection diag ram for the ad7656 - 1/ ad7657 - 1/ad7658 - 1 , illustrating the reduction in the number and value of decoupling capacitors that are required . there are e ig ht av cc supply pins on each part . t he av cc suppl ies are the supplies used for the ad7656 - 1/ad7657 - 1/ad7658 - 1 conversion process; therefore, they should be well decoupled. the av cc supply which is applied to eight av cc pins can be decoupled using just one 1 f capacitor . the ad7656 - 1/ad7657 - 1/ad7658 - 1 can operate with the internal reference or an externally appl ied reference. in this configuration, the parts are configured to operate with the external reference. the refin/refout pin is decoupled with a 1 f capacitor. the three internal reference buffers are enabled. each of the refcap x pins is decoupled with a 1 f capacitor . if the same supply is being used for the av cc and dv cc suppl ies , place a ferrite or small rc filter between the supply pins. agnd pins are connected to the agnd plane of the system. the dgnd pins are connected to the digital ground plane i n the system. connect t he agnd and dgnd planes together at one place in the system. this connection should be as close as possible to the ad7656 - 1/ad7657 - 1/ad7658 - 1 in the system. table 9 . lsb size for each analog input range para meter input range for ad7656 - 1 input range for ad7657 - 1 input range for ad7658 - 1 10 v 5 v 10 v 5 v 10 v 5 v lsb size 0.305 mv 0.152 mv 1.22 mv 0.610 mv 4.88 mv 2.44 mv fs range 20 v/65,536 10 v/65,536 20 v/16 , 384 10 v/16 , 384 20 v/4096 10 v/4096
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 22 of 32 + + + dv cc + dv cc av cc agnd dgnd v drive dgnd v dd agnd + v s s agnd + + refcapa, b, c agnd refin/out agnd d0 to d15 convst a, b, c cs rd busy ser/par h/s w/b range reset stby v drive ad7656-1/ ad7657-1/ ad7658-1 1f p/c/dsp 1f 1f 1f 1f 1f 1f digital supply voltage +3v or +5v ana l o g supply voltage 5v 1 see power supply configuration section. +9.5v to +16.5v 1 supply 2.5v ref six analog inputs ?9.5v to ?16.5v 1 supply parallel interface 07017-026 figure 28 . typical connection diagram the v drive supply is connected to the same supply as the processor. the voltage on v drive controls the voltage value of the output logic signals. decouple t he v dd and v ss signals with a mi nimum 1 f decoupling capacitor. these supplies are used for the high voltage analog input structures on the ad7656 - 1/ad7657 - 1/ad7658 - 1 analog inputs. driving the analog i nputs together, the driver amplifier and the analog input circuit used for the ad765 6 - 1 must settle for a full - scale step input to a 16 - bit level (0.0015%), which is within the specified 550 ns acquisition time of the ad7656 - 1. the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transiti on noise performance of the ad7656 - 1. in addition, t he driver also needs to have a thd performance suitable for the ad7656 - 1. the ad8021 meets these requirements. the a d8021 needs an external compensation capacitor of 10 pf. if a dual version of the ad8021 is required, the ad8022 can be used. the ad8610 and the ad797 can also be used to drive the ad7656 - 1/ad7657 - 1/ ad7658 - 1. interface options the ad7656 - 1/ad7657 - 1/ad7658 - 1 provide two interface options: a high speed parallel interface and a high sp eed serial interface. the required interface mode is selected via the ser/ pa r sel pin. the parallel interface can operate in word ( w /b = 0) or byte ( w /b = 1) mode. when in serial mode , the ad7656 - 1/ad76 57- 1/ad7658 - 1 can be configured into da isy - chain mode. when in parallel mode, a read operation only access es the results related to conversions which have just occurred. for example, consider the case where convst a and convst c are toggled simultaneously but convst b is not used. at end of the conversion process when busy goes low a read is implemented. four read pulses (in parallel mode) are applied and data from v1, v2, v5, and v6 are output. data from v 3 and v4 is not output since convst b was not togg led in this cycle . however, when in serial mode all zeros are output in place of the adc result for adcs not included in the conversion cycle. see the serial interface section for more information. parallel interface (ser/ par sel = 0) th e ad7656 - 1/ad7657 - 1/ad7658 - 1 consist of six 16 - /14 - / 12- bit adcs , respectively. a simultaneous sample of all six adcs can be performed by connecting all three convst pins ( convst a, convst b, and convst c ) together . the ad7656 - 1/ad7657 - 1/ ad7658 - 1 need to see a convst pulse to initiate a conversion; this should consist of a falling convst edge followed by a rising convst edge . the rising edge of convst initiates simultaneous conversions on the selected adcs. the ad7656 - 1/ad7657 - 1/ad7658 - 1 each contain an on - chip oscillator that is used to perform the conversions. the conversion time, t conv , is 3 s. the busy signal goes low to indicate the end of a conversion. the falling edge of the busy signal is used to place the track - and - hold amplifier into track mode. the ad7656 - 1/ad7657 - 1/ad7658 - 1 also allow the six adcs to be converted simultaneously in pairs by pulsing the three convst pins independently. convst a is used to initiate simultaneous conversions on v1 and v2, convst b is used to initiate simultaneous co nversions on v3 and v4, and convst c is used to initiate simultaneous conversions on v5 and v6. the conversion results from the simultaneously sampled adcs are stored in the output data registers. note that once a rising edge occurs on any one convst pin t o initiate a conversion , then any
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 23 of 32 further convst rising edges on any of the convst pins are ignored while busy is high. data can be read from the ad7656 - 1/ad7657 - 1/ad7658 - 1 via the parallel data bus with standard cs and r d signals ( w /b = 0). to read the data over the parallel bus, tie ser/ pa r sel low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines db0 to db15 leave their high impedance state when both cs and rd are logic low. the cs signal can be permanently tied low, and the rd signal can be used to access the conversion results. a read operation can take place after the busy signal goes low. the number of required read operations depends on the number of adcs that are simultaneously sampled (see figure 29 ). if convst a and convst b are simultaneously brought low, four read operations are required to obtain the conversion results from v1, v2, v3, and v4. if convst a and convst c are simultaneously brought low, four read operations are required to obtain the conversion results from v1, v2, v5, and v6. the conversion results are output in ascending order. for the ad7657 - 1 , db15 and db14 contain two leading 0 s, and db[13:0] output the 14 - bit conversion result. for the ad7658 - 1 , db[15:12] contain four leading 0 s, and db[11:0] output the 12- bit conversion result. when using the three convst signals to independently initiate conversions on the three adc pairs, once a rising edge occurs on any one convst pin to initiate a conversion then any further convst rising edges on any of the convst pins are ignored while busy is high. although a conversion can be initiated during a read sequence, it is not recommended practice, because doing so may affect the performance of the conversion. for the specified performance, it is recommended to perfor m the read after the conversion. for unused input chann el pairs, tie the associated convst pin to v drive . if there is only an 8 - bit bus available, the ad7656 - 1/ad7657 - 1/ ad7658 - 1 parallel interface can be configured to operate in byte mode ( w /b = 1). in this configuration, the db7/hben/dcen pin takes on its hben function. each channel conversion result from the ad7656 - 1/ad7657 - 1/ad7658 - 1 can be accessed in two read operations, with eight bits of data provided on db15 to db8 for each of th e read operations (see figure 30 ). the hben pin determines whether the read operation first accesses the high byte or the low byte of the 16 - bit conversion result. to always access the low byte first on db15 to db8, tie the hben pin low. to always access the high byte first on db15 to db8, tie the hben pin high. in byte mode when all three convst pins are pulsed together to initiate simultaneous conversions on all six adcs, 12 read operations are necessary to read back the six 1 6 - /14 - /12 - bit conversion results. db[6:0] should be left unconnected in byte mode. v1 v2 v3 v4 v5 v6 convst a, convst b, convst c busy cs rd data t quiet t 7 t 8 t 9 t 4 t 2 t 3 t 5 t 6 t acq t conv t 10 07017-027 figure 29 . parallel interface timing diagram ( w /b = 0) low byte high byte db15 to db8 cs rd t 3 t 6 t 7 t 8 t 4 t 5 t 9 07017-028 figure 30 . parallel interface read cycle fo r byte mode of operation ( w /b = 1, hben = 0)
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 24 of 32 software selection o f adcs the h /s sel pin determines the source of the combination of adcs that are to be simultaneously sampled. when the h /s sel pin is logic low, the combination of channels to be simultaneously sampled is determined by the convst a, convst b, and convst c pins. when the h /s sel pin is logic high, the combination of channels selected for simultaneous sampling is determ ined by the contents of the db15 to db13 control registers . in this mode, a write to the control register is necessary. the control register is an 8 - bit write - only register. data is written to this register using the cs and wr pins and the db[15:8] data pins ( see figure 31 ). the control register is detailed in table 10 and table 11 . to select an adc pair to be simultaneously sampled, set th e corresponding data line high during the write operation. data db15 to db8 cs t 13 t 15 t 14 t 11 t 12 wr 07017-029 figure 31 . parallel interface write cycle for word mode ( w /b = 0) the ad7656 - 1/ad7657 - 1/ad7658 - 1 control register allows individual ranges to be progra mmed on each adc pair. db12 to db10 in the control register are used to program the range on each adc pair. after a reset occurs on the ad7656 - 1/ad7657 - 1/ad7658 - 1, the control register contains all 0 s. the convst a signal is used to initiate a simultaneo us conversion on the combination of channels selected via the control register. the convst b and convst c signals can be tied low when operating in software mode ( h /s sel = 1). the number of read pulses required depends on the number of a dcs selected in the control register and on whether the devices are operating in word or byte mode. the conversion results are output in ascending order. during the write operation, data bus bit db15 to data bus bit db8 are bidirectional and become inputs to the control register when rd is logic high and cs and wr are logic low. the logic state on db15 through db8 is latched into the control register when wr goes logic high. table 10 . control register bit map 1 db15 db14 db13 db12 db11 db10 db9 db8 vc vb va rngc rngb rnga refen refbuf 1 default a ll 0s. table 11. control register bit function descriptions bit mnemonic description db15 vc this bit is used to select the v5 and v6 analog inputs for the next conversion. when this bit is set to 1, v5 and v6 are simultaneously converted on the next convst a rising edge. db14 vb this bit is used to select the v3 and v4 analog inputs for the n ext conversion. when this bit is set to 1, v3 and v4 are simultaneously converted on the next convst a rising edge. db13 va this bit is used to select the v1 and v2 analog inputs for the next conversion. when this bit is set to 1, v1 and v2 are simultaneo usly converted on the next convst a rising edge. db12 rngc this bit is used to select the analog input range for the v5 and v6 analog inputs . when this bit is set to 1, the 2 v ref range is selected for the next conversion. when this bit is set to 0, th e 4 v ref range is selected for the next conversion. db11 rngb this bit is used to select the analog input range for the v3 and v4 analog inputs . when this bit is set to 1, the 2 v ref range is selected for the next conversion. when this bit is set t o 0, the 4 v ref range is selected for the next conversion. db10 rnga this bit is used to select the analog input range for the v1 and v2 analog inputs . when this bit is set to 1, the 2 v ref range is selected for the next conversion. when this bit is set to 0, the 4 v ref range is selected for the next conversion. db9 refen this bit is used to select the internal reference or an external reference. when this bit is set to 0, the external reference mode is selected. when this bit is set to 1, the in ternal reference is selected. db8 refbuf this bit is used to select between using the internal reference buffers and choosing to bypass these reference buffers. when this bit is set to 0, the internal reference buffers are enabled and decoupling is requir ed on the refcap x pins. when this bit is set to 1, the internal reference buffers are disabled and a buffered reference should be applied to the refcap x pins.
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 25 of 32 changing the analog input range ( h /s sel = 0) the ad7656 - 1/ad7657 - 1/ad7658 - 1 range pin allows the user to select either 2 v ref or 4 v ref as the analog input range for the six analog inputs. when the h /s sel pin is low, the logic state of the range pin is sampled on the falling edge of the busy signal to de termine the range for the next simultaneous conversion. when the range pin is logic high at the falling edge of the busy signal, the range for the next conversion is 2 v ref . when the range pin is logic low at the falling edge of the busy signal, the r ange for the next conversion is 4 v ref . after a reset pulse, the range is updated on the first falling busy edge. changing the analog input range ( h /s sel = 1) when the h /s sel pin is high, the range can be changed by writing to the control register. db[12:10] in the control register are used to select the analog input ranges for the next conversion . each analog input pair has an associated range bit, allowing independent ranges to be programmed on each adc pair. wh en the rngx bit is set to 1, the range for the next conversion is 2 vref. when the rngx bit is set to 0, the range for the next conversion is 4 vref. serial interface (ser/ par sel = 1) by pulsing one , two, or all three convst signa ls, the ad7656 - 1/ ad7657 - 1/ad7658 - 1 use their on - chip trimmed oscillator to simultaneously convert the selected channel pairs on the rising edge of convst. after the rising edge of convst , the busy signal goes high to indicate that the conversion has start ed. it returns low when the conversion is complete , 3 s later. any further convst rising edg es on either convst a, convst b, or convst c are ignored as long as busy is high. the output register is loaded with the new conversion results, and data can be re ad from the ad7656 - 1/ad7657 - 1/ad7658 - 1. to read the data back from the parts over the serial interface, ser/ pa r sel should be tied high. the cs and sclk signals are used to transfer data from the ad7656 - 1/ad7657 - 1/ad7658 - 1. the parts have three dout pins : dout a, dout b, and dout c. data can be read back from each part using one, two, or all three dout lines. figure 32 shows six simultaneous conversions and the read sequence using three dout lines. also in figure 32 , 32 sclk transfers are used to access data from the ad7656 - 1/ad76 57- 1/ ad7658 - 1; however, two 16 - sclk individually framed transfers with the cs signal can also be used to access the dat a on the three dout lines. any additional sclks applied after this result in an output of all zeros. when the serial interface is selected and conversion data is clocking out on all three dout lines, tie db0/sel a, db1/sel b, and db2/sel c to v drive . these pins are used to enable the dout a to dout c lines, respectively. if it is required to clock conversion data out on two data out put lines, use dout a and dout b. to enable dout a and dout b, tie db0/sel a and db1/sel b to vdrive , and db2/sel c should be t ied low. when six simultaneous conversions are performed and onl y two dout lines are used, a 48 - sclk transfer can be used to access the data from the ad7656 - 1/ ad7657 - 1/ad7658 - 1. any additional sclks applied after this result in an output of all zeros. the read sequence is shown in figure 33 for a simultaneous conversion on all six adcs using two dout lines. if a simultaneous conversion occurred on all six adcs, and only two dout lines are used to read the results from the ad7656 - 1/ad7657 - 1/ad7658 - 1 , dout a clocks out the result from v1, v2, and v5, wh ereas dout b clocks out the results from v3, v4, and v6. data can also be clocked out using just one dout line, in which case use dout a to access the conversion data. to configure t he ad7656 - 1/ad7657 - 1/ad7658 - 1 to operate in this mode, tie db0/sel a to v drive , and tie db1/sel b and db2/sel c low. the disadvantage of using only one dout line is that the throughput rate is reduced. data can be accessed from the ad7656 - 1/ad7657 - 1/ad7658 - 1 using one 96 - sclk transfer, three 32 - sclk individually framed transfers, or six 16 - sclk individually framed transfers. any additional sclks applied after this result in an output of all zeros. when using the serial interface , tie the rd signal low and leave t he unused dout line(s) unconnected. whether one, two , or three data output lines are used, if a particular convst pin is not used in the conversion cycle then all zeros are output in place of the adc result for the associated adcs even though they were not used in the conversion cycle. this means t hat if, for example , only convst b is pulsed and one da ta output pin is in use , then 64 sclks are r equired to access the results f r om v3 and v4 , but only 32 sclks are required if two or t hree data output lines are in use. serial read operatio n figure 34 shows the timing diagram for reading data from the ad7656 - 1/ad7657 - 1/ad7658 - 1 when the serial interface is selected . the sclk input signal provides the clock so urce for the serial interface. the cs signal goes low to access data from the ad7656 - 1/ad7657 - 1/ad7658 - 1. the falling edge of cs takes the bus out of three - state and clocks out the msb of the 16- bit conversion result. th e adcs output 16 bits for each conversion result; the data stream of the ad7656 - 1 consists of 16 bits of conversion data , provided msb first. the data stream for the ad7657 - 1 consists of two leading 0 s followed by 14 bits of conversion data , provided msb f irst. the data stream for the ad7658 - 1 consists of four leading 0 s and 12 bits of conversion data , provided msb first.
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 26 of 32 the first bit of the conversion result is valid on the first sclk falling edge after the cs falling edge. the subsequ ent 15 data bits are clocked out on the rising edge of the sclk signal. data is valid on the sclk falling edge. to access each conversion result, 16 clock pulses must be provided to the ad7656 - 1/ad7657 - 1/ ad7658 - 1. figure 34 sho ws how a 16 - sclk read is used to access the conversion results. v1 v2 convst a, convst b, convst c busy cs dout a dout b dout c 32 v3 v4 v5 v6 sclk 16 t quiet t acq t conv 07017-030 figure 32 . serial interface with three dout lines v1 v2 v5 dout a dout b 48 v3 v4 v6 sclk cs 07017-031 figure 33 . serial interface with two dout lines busy acquisition conversion acquisition sclk cs dout a, dout b, dout c db15 db14 db13 db1 db0 t acq t 10 t conv t 2 t 1 t quiet t 21 t 20 t 17 t 16 t 18 t 19 convst a, convst b, convst c 07017-032 figure 34 . serial read operation
data sheet ad7656-1/ad7657-1/ad7658-1 rev. d | page 27 of 32 daisy-chain mode (dcen = 1, ser/par sel = 1) when reading conversion data back from the ad7656-1/ad7657-1/ ad7658-1 using one/two/three dout pins, it is possible to configure the parts to operate in daisy-chain mode by using the dcen pin. this daisy-chain feature allows multiple ad7656-1/ ad7657-1/ad 7658-1 devices to be cascaded together and is useful for reducing the component count and wiring connections. an example connection of two devices is shown in figure 36. this configuration shows two dout lines being used for each device. simultaneous sampling of the 12 analog inputs is possible by using a common convst signal. the db5, db4, and db3 data pins are used as the dcin[a:c] data input pins for the daisy-chain mode. the rising edge of convst is used to initiate a conversion on the ad7656-1/ad7657-1/ad7658-1. after the busy signal has gone low to indicate that the conversion is complete, the user can begin to read the data from the two devices. figure 37 shows the serial timing diagram when operating two ad7656-1/ad7657-1/ ad7658-1 devices in daisy-chain mode. the cs falling edge is used to frame the serial transfer from the ad7656-1/ad7657-1/ad7658-1 devices, to take the bus out of three-state, and to clock out the msb of the first conversion result. in the example shown in figure 37, all 12 adc channels are simultaneously sampled. two dout lines are used to read the conversion results in this example. cs frames a 96-sclk transfer. during the first 48 sclks, the conversion data is transferred from device 2 to device 1. dout a on device 2 transfers conversion data from v1, v2, and v5 into dcin a in device 1; dout b on device 2 transfers conversion results from v3, v4, and v6 to dcin b in device 1. during the first 48 sclks, device 1 transfers data into the digital host. dout a on device 1 transfers conversion data from v1, v2, and v5; dout b on device 1 transfers conversion da ta from v3, v4, and v6. during the last 48 sclks, device 2 clocks out 0s, and device 1 shifts the data clocked in from device 2 during the first 48 sclks into the digital host. this example can also be implemented using six 16-sclk individually framed transfers if dcen remains high during the transfers. figure 38 shows the timing if two ad7656-1/ad7657-1/ad7658- 1 devices are configured in daisy-chain mode and are operating with three dout lines. assuming that a simultaneous sampling of all 12 inputs occurs, the cs frames a 64 sclk transfer during the read operation. during the first 32 sclks of this transfer, the conversion results from device 1 are clocked into the digital host and the conversion results from device 2 are clocked into device 1. during the last 32 sclks of the transfer, the conversion results from device 2 are clocked out of device 1 and into the digital host, and device 2 clocks out 0s. the maximum number of devices in the chain is limited by the throughput required per channel depending on the application needs, the sclk frequency used, and the number of serial data lines used. standby/partial power-down modes of operation (ser/ par sel = 0 or 1) each adc pair can be individually placed into partial power- down mode at the end of their conversion by bringing the associated convst signal low before the falling edge of busy. if a convst pin is low when busy goes low, the associated adc pair only enters partial power-down mode if they were actually converting within that cycle, that is, if that particular convst pin was used to trigger conversions. to power an adc pair back up, the convst signal should be brought high to tell the adc pair to power up and place the track-and-hold amplifier into track mode. after the power-up time from partial power-down has elapsed, the convst signal can receive a rising edge to initiate a valid conversion. in partial power-down mode, the reference buffers remain powered up. when an adc pair is in partial power-down mode, conversions can still occur on the other fully powered adcs. in figure 35 at point a, adc 1 and adc 2 enter partial power-down while adc 3 to adc 6 remain fully powered. at point b in figure 35, adc1 and adc 2 begin to power up. once the required power up time has elapsed then a conversion can be initiated on the next convst rising edge as shown. 07017-135 a convst a t wake-up busy convst b convst c b figure 35. entering and exiting partial power-down mode the ad7656-1/ad7657-1/ad7658-1 have a standby mode whereby the devices can be placed into a low power consumption mode (315 w maximum). the ad7656-1/ad7657-1/ad7658-1 are placed into standby mode by bringing the input stby logic low and can be powered up again for normal operation by bringing stby logic high. the output data buffers are still operational when the ad7656-1/ad7657-1/ad7658-1 are in standby mode, meaning the user can continue to access the conversion results of the parts. this standby feature can be used to reduce the average power consumed by the ad7656-1/ad7657-1/ ad7658-1 when operating at lower throughput rates. the parts can be placed into standby at the end of each conversion when busy goes low and are taken out of standby mode prior to the next conversion. the time for the ad7656-1/ad7657-1/ ad7658-1 to come out of standby is called the wake-up time. the wake-up time limits the maximum throughput rate at which the ad7656-1/ad7657-1/ad7658-1 can operate when powering down between conversions. see the specifications section.
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 28 of 32 digital host convert cs sclk ad7656-1/ ad7657-1/ ad7658-1 ad7656-1/ ad7657-1/ ad7658-1 convst convst cs cs sclk sclk data in1 data in2 dout a dout b dout a dout b dcin a dcin b dcen = 1 device 1 dcen = 0 device 2 07017-033 figure 36 . daisy - chain configuration 07017-034 device 1, dout a msb v1 lsb v1 msb v2 lsb v2 msb v5 lsb v5 msb v1 lsb v1 msb v2 lsb v5 msb v1 lsb v1 msb v2 lsb v2 msb v5 lsb v5 1 2 3 busy sclk cs 15 16 17 31 32 33 47 48 49 63 65 64 94 95 96 device 1, dout b msb v3 lsb v3 msb v4 lsb v4 msb v6 lsb v6 msb v3 lsb v3 msb v4 lsb v6 device 2, dout a msb v3 lsb v3 msb v4 lsb v4 msb v6 lsb v6 device 2, dout b convst a, convst b, convst c figure 37 . daisy - chain serial interface timing with two dout lines device 1, dout a msb v1 lsb v1 msb v2 lsb v2 msb v1 lsb v1 msb v2 lsb v2 msb v1 lsb v1 msb v2 lsb v2 1 2 3 busy sclk cs 15 16 17 31 32 33 47 48 49 63 64 device 2, dout a msb v3 lsb v3 msb v4 lsb v4 device 2, dout b device 1, dout b msb v3 lsb v3 msb v4 lsb v4 msb v3 lsb v3 msb v4 lsb v4 device 1, dout c msb v5 lsb v5 msb v6 lsb v6 msb v5 lsb v5 msb v6 lsb v6 msb v5 lsb v5 msb v6 lsb v6 device 2, dout c convst a, convst b, convst c 07017-035 figure 38 . daisy - chain serial interface timing with three dout lines
data sheet ad7656- 1/ad7657 - 1/ad7658 - 1 rev. d | page 29 of 32 application hints layout design t he printed circuit board (pcb) that houses the ad7656 - 1/ ad7657 - 1/ ad7658 - 1 so that the analog and digital sections are separated and confined to different areas of the board. use a t least one ground plane. it can be common or split between the digital and analog sections. in the case of the split plane, join the digital and analog ground i n only one place, preferably underneath the ad7656 - 1/ ad7657 - 1/ad7658 - 1, or at least as close as possible to the part. if the ad7656 - 1/ad7657 - 1/ad7658 - 1 are in a system where multiple devices require analog - to - digital ground connections, the connection sh ould still be made at only one point, a star ground point, established as close as possible to the ad7656 - 1/ ad7657 - 1/ad7658 - 1 . make g ood connections to the ground plane. avoid sharing one connection for multiple ground pins. individual vias or multiple vi as to the ground plane should be used for each ground pin. avoid running digital lines under the devices because doing so couples noise onto the die. allow t he analog ground plane to run under the ad7656 - 1/ad7657 - 1/ad7658 - 1 to avoid noise coupling. shield f ast - switching signals like convst or clocks with digital ground to avoid radiating noise to other sections of the board, and the fast switching signals should never run near analog signal paths. avoid c rossover of digital and analog signals . traces on la yers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. the power supply lines to the av cc , dv cc , v drive , v dd , and v ss pins on the ad7656 - 1/ad7657 - 1/ad7658 - 1 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. establish g ood connections between the ad7656 - 1/ad7657 - 1/ad7658 - 1 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. good decoupling is also important to lower the supply impedance presented to the ad7656 - 1/ad7657 - 1/ad7658 - 1 and to reduce the magnitude of the supply spikes. place t he decoupling capacitors close to, ideal ly right up against, these pins and their corresponding ground pins. additionally, place low esr 1 f capacitors on each of the supply pins, the refin /ref out pin, and each refcap x pin. avoid sharing these capacitors between pins , and u se vias to connect th e capacitors to the power and ground planes . in addition, u se wide, short traces between each via and the capacitor pad, or place the via s adjacent to the capacitor pad to minimize parasitic inductances. the ad7656 - 1/ad7657 - 1 / ad7658 - 1 offer the user a red uced decoupling solution that is pin and software compatible with ad7656/ad7657/ad7658 . the r ecommended reduced decouplin g required for ad7656 - 1/ ad7657 - 1/ad7658 - 1 is outlined in figure 28. power supply configu ration as outlined in the absolute maximum ratings section, the analog inputs should not be applied to the ad7656 - 1 / ad7657 - 1 /ad7658 - 1 until after the ad7656 - 1 /ad7657 - 1 / ad7658 - 1 power supplies have been applied to the device. however, if a condition exists where the system analog signal conditioning circuitry supplies are different to the v dd and v ss supplies of the ad7656 - 1 /ad7657 - 1 /ad7658 - 1 , or if the analog inputs may be applied prior to the ad7656 - 1 / ad7657 - 1 /ad7658 - 1 supplies being established , then an analog input series resister and schottky diodes in series with the v dd and v ss supplies are recom mended ( s ee figure 39) . this configuration should also be used if av cc is applied to the ad7656 - 1 /ad7657 - 1 /ad7658 - 1 prior to v dd and v ss being applied . v1 v dd v ss v ss v dd 240? analog inputs v2 v3 ad7656-1/ ad7657-1/ ad7658-1 v4 v5 v6 07017-037 figure 39 . power supply configuration
data sheet ad7656-1/ad7657-1/ad7658-1 rev. d | page 30 of 32 outline dimensions compliant to jedec standards ms-026-bcd 051706-a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 11.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 0 . 1 5 0 . 0 5 7 3.5 0 figure 40. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model 1 notes temperature range packag e description package option ad7656bstz-1 ?40c to +85c 64-lead low pr ofile quad flat package [lqfp] st-64-2 ad7656bstz-1-rl ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656ystz-1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656ystz-1-rl ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657bstz-1 ?40c to +85c 64-lead low pr ofile quad flat package [lqfp] st-64-2 ad7657bstz-1-rl ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657ystz-1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657ystz-1-rl ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658bstz-1 ?40c to +85c 64-lead low pr ofile quad flat package [lqfp] st-64-2 ad7658bstz-1-rl ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658ystz-1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658ystz-1-rl ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 eval-ad7656-1cbz 2 evaluation board eval-ad7657-1cbz 2 evaluation board eval-ad7658-1cbz 2 evaluation board eval-control brd2z 3 controller board 1 z = rohs compliant part. 2 this can be used as a standalone evaluation board or in conjunction with the eval-control board for evaluation/demonstration p urposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices, inc., evaluation boards ending in the cb designators. to order a complete evaluation kit, the particular adc evaluation boar d, for example, eval-ad7656-1/ad7657-1/ad7658-1cb, the eval-control brd2, and a 12 v transformer must be ordered. see the relevant evaluation board technical note for more information.
data sheet ad7656-1/ad7657-1/ad7658-1 rev. d | page 31 of 32 notes
ad7656- 1/ad7657 - 1/ad7658 - 1 data sheet rev. d | page 32 of 32 notes ? 2008 C 2012 analog devices, inc. all rights rese rved. trademarks and registered trademarks are the property of their respective owners. d07017 - 0 - 3/12(d)

▲Up To Search▲

Price & Availability of AD7657-1-15

	To Download AD7657-1-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .